1. Field of the Invention
The present invention relates to an apparatus for driving a plasma display panel, and more particularly to an apparatus for driving a plasma display panel, with a simple structure.
2. Description of the Background Art
FIG. 1 illustrates a general AC (Alternative Current) surface-discharge plasma display panel. The PDP includes front and rear transparent glass substrates 122 and 124 which are 100 to 200 .mu.m away from each other in parallel. Partition walls 126 are formed on the rear substrate 124 through a thick film printing technique at intervals of 400 .mu.m, leaving a space between the front and rear substrates 122 and 124. Each of the partition walls 1 26 is 50 .mu.m in width.
Column electrodes Xj (where j−1, 2, . . . , m) of X electrodes made of aluminum (Al) or an Al alloy are formed between the partition walls 126 to perform an address function. The column electrodes Xj are parallel to the partition walls 126 and has a thickness of 100 nm. RGB florescent material layers are coated over the respective X electrodes Xj to a thickness of 10 to 30 nm to form light emitting layers 136.
Row electrodes Yi and Zi (where i=1, 2, . . . , n) of Y and Z electrodes perpendicular to the X electrodes are formed on the front substrate 122. The electrodes Yi and Zi are extended in parallel to a thickness of a few hundred nm by the deposition of ITO Indium tin Oxide) or SnO (tin oxide). The adjacent row electrodes Yi and Zi constitute row-electrode pairs (Yi, Zi).
Metal bus electrodes .alpha.i and .beta.i narrower than the row electrodes Yi and Zi are closely formed to the row electrodes Yi and Zi. These bus electrodes .alpha.i and .beta.i are auxiliary electrodes for making up for the row electrodes Yi and Zi having weak conductivity.
In order to protect these row electrodes Yi and Zi, a dielectric layer 130 is formed to a thickness of 20 to 30 .mu.m. An MgO layer 132 is coated over the dielectric layer 130 to a thickness of a few hundred nm.
After the electrodes Xj, Yi, Zi, .alpha.i and .beta.i, the dielectric layer 130 and the light emitting layers 136 are formed, the front and rear substrates 122 and 124 are sealed up and the gas of a discharge space 128 is ejected. Then, moisture is removed from the surface of the MgO layer 132 by baking. Next, inert mixture gas including 3 to 7 percent NeXe gas is injected into the discharge space 128 by 400 to 600 torr.
A unit light emitting region is defined as one pixel P(i, j) based on an intersection of the row electrodes Yi and Zi and the column electrodes Xj. If a wall voltage is formed by an addressing discharge between the electrodes Xj and Yi, a sustaining pulse is applied between the electrodes Yi and Zi to maintain a discharge. Therefore, the luminescent material layer 136 is excited to emit light. Moreover, a light emitting operation is controlled through selection, sustenance and erasure of a light emitting discharge of the pixel P(i, j) by a voltage applied between the electrodes Xj, Yi and Zi.
FIG. 2 is a block diagram showing a driving apparatus for a general plasma display panel. Referring to FIG. 2, a signal processor 210 converts an external image signal into image data suitable for driving the PDP.
A data arranger 220 reconstructs the image data of one TV field to a plurality of sub-fields in order to process the gray scale of the image data converted by the signal processor 210.
An X-electrode driver 230 and a Y-electrode driver 240 respectively apply to X and Y electrodes address and scan pulses for forming a wall voltage on a discharge cell of the plasma display panel. The Y-electrode driver 240 and a Z-electrode driver 250 alternatively apply to Y and Z electrodes a sustain pulse for maintaining the discharge of a discharge cell on which the wall voltage is formed.
A main controller 260 performs a control operation to sequentially read the image data reconstructed by the data arranger 20 according to the external image signal and to be supplied to the X-electrode driver 230 one scan line by one scan line. Moreover, the main controller 260 supplies a logic control pulse to a high-voltage driving circuit 270.
The high-voltage driving circuit 270 receives the logic control pulse from the main controller 260 and supplies a high-voltage control pulse to the X-electrode, Y-electrode and Z-electrode drivers 230, 240 and 250.
FIG. 3 shows the relationship between the data arranger 220 and the X-electrode driver 230 illustrated in FIG. 2. FIG. 4 shows waveforms for driving data integrated circuits (ICs) of the X-electrode driver 230 illustrated in FIG. 3.
As shown in FIG. 3, the X-electrode driver 230 includes data ICs 310 for respectively processing one-frame image data reconstructed to a plurality of sub-fields by the data arranger 220.
The data ICs 310 receive control data corresponding to one scan line from the main controller 260.
Each of the data ICs 310 has 6 input pins and 96 output pins and receives the control data from the main controller 260 through the 6 input pins. In order to generate 96 outputs from 6 inputs, each of the data ICs 310 necessitates 16 address clocks per scan line.
The data arranger 220 includes a first temporary storage 221, for example, a shift register for sequentially storing control data of one scan line, and a second temporary storage 223, for example, a latch for sending the control data of one scan line stored in the first temporary storage 221 at a predetermined time.
The number of pins of an output terminal of the second temporary storage 223 is closely related to the number of input pins of each of the data ICs 310. That is, an input terminal of each of the data ICs 310 for receiving the control data of one scan line from the second temporary storage 223 at a predetermined time has 6 pins. Moreover, since data is transmitted in parallel to the data ICs 310 from the second temporary storage 223, the number of pins of the output terminals of the second temporary storage 223 is 6 times the number of the data ICs 310.
For example, an XGA Extended Graphics Array) resolution display size of 1366.times.768 pixels is 4098 (=1366.times.3 (RGB)) in the total number of pixels. Since the required number of the data ICs is generally 22, the number of pins of the output terminal of the second temporary storage 223 is 132 (=22.times.6).
When the control data of one scan line is transmitted in parallel, the number of pins of the output terminal of the second temporary storage 223 becomes large. Furthermore, since the first temporary storage 221 should store all the control data of one scan line, the storage capacity of the first temporary storage 221 should be large enough to store n.times.6 bits (where n is the number of data ICs). In this case, the 6 bits means the amount of control data transmitted to drive one data IC 310 having 6 input pins.